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lvds interface ics 35bit lvds transmitter 35:5 serializer BU8254KVT description lvds interface ic of rohm "serializer" "deserializer " operate from 8mhz to 150mhz wide clock range, and number of bits range is from 35 to 70. data is transm itted seven times (7x) stream and reduce cable number by 3(1/3) or less. the rohm's lvds has low swing mode to be able to expect further low emi. features 35bits data of parallel lvcmos level inputs are converted to fi ve channels of lvds data stream. 30bits of rgb data and 5bits of timing and control data(hsync,v sync,de,cntl1,cntl2) are transmitted up to 784mbps effective rate per lvds channel. support clock frequency from 8mhz up to 112mhz. support consumer video format including 480i, 480p, 720p and 10 80i as well. clock edge selectable power down mode support spread spectrum clock generator. support reduced swing lvds for low emi. 30bit lvds receiver is reco mmended to use bu8255kvt. applications flat panel display precaution this chip is not designed to protect from radioactivity. the chip is made strictly for the specific application or equip ment. then it is necessary that the unit is measured as need. this document may be used as strategic technical data which sub jects to cocom regulations. status of this document the japanese version of this document is the official specifica tion. please use the translation version of this document as a refere nce to expedite understanding of the official version. if there is any uncertainty in translation version of this docu ment, official version takes priority. jun.2008
2 / 20 block diagram figure-1 block diagram pll tclk p/n (8 112mhz) ta p/n rs rf xrst lvds output ta6-ta0 7 tb p/n tb6-tb0 tc p/n tc6-tc0 td p/n td6-td0 te p/n te6-te0 parallel to serial lvcmos input parallel to serial parallel to serial parallel to serial parallel to serial 7 7 7 7 clkin (8112mhz)
3 / 20 tqfp64v package outline and specification figureC2 tqfp64v package outline and specification BU8254KVT lot no. 1pin mark product no.
4 / 20 pin configuration figure-3 pin diagram (top view) tb5 tb4 gnd tb3 tb2 rs tb1 tb0 ta6 gnd ta5 ta4 ta3 ta2 ta1 ta0 lvds gnd tan tap tbn tbp lvds vdd lvds gnd ten tep lvds gnd pll vdd te6 td4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin tqfp (top view) td3 tcn tcp tclkn tclkp tdn tdp pll gnd xrst clk in te5 gnd te4 te3 vdd te2 te1 te0 td6 gnd td5 td2 td1 rf tdo tc6 tc5 gnd tc4 tc3 tc2 tc1 vdd tc0 tb6
5 / 20 pin description table 1 : pin description pin name pin no. type descriptions tap, tan 30,31 lvds out lvds data out. tbp, tbn 28,29 lvds out tcp, tcn 24,25 lvds out tdp, tdn 20,21 lvds out tep, ten 18,19 lvds out tclkp, tclkn 22,23 lvds out lvds clock out. ta0ta6 33,34,35,36,37,38,40 in pixel data inputs. tb0tb6 41,42,44,45,46,48,49 in tc0tc6 50,52,53,54,55,57,58 in td0td6 59,61,62,63,64,1,3 in te0te6 4,5,6,8,9,11,16 in xrst 13 in h : normal operation, l : power down (all outputs are hi-z) rs 43 in lvds swing mode, v ref * 1 select. rs lvds swing small swing input support v dd 350mv n/a 0.61.4v 350mv rs-v ref gnd 200mv n/a *1 v ref is input reference voltage. rf 60 in input clock triggering edge select. h : rising edge, l : falling edge. vdd 51,7 power power supply pins for lvcmos inputs and digital core. clkin 12 in clock input. gnd 2,10,39,47,56 ground ground pins for lvcmos inputs and digital core. lvds vdd 27 power power supply pins for lvds outputs. lvds gnd 17,26,32 ground ground pins for lvds outputs. pllvdd 15 power power su pply pin for pll core. pllgnd 14 ground ground pins for pll core.
6 / 20 electrical characteristics rating table 2 : absolute maximum rating parameter symbol rating units min max supply voltage v dd -0.3 4.0 v input voltage v in -0.3 v dd +0.3 v output voltage v out -0.3 v dd +0.3 v storage temperature range tstg -55 125 table 3 : package power package power dissipation (mw) de-rating (mw/) *1 tqfp64v 700 7.0 1000 *2 10.0 *2 *1:at temperature ta >25 *2:package power when mounting on the pcb board. the size of pcb board :70701.6mm 3 the material of pcb board :the fr 4 glass epoxy board.(3% or les s copper foil area) (it is recommended to apply the ab ove package power requirement to pcb board when the small swing input mode is used) table 4 : recommended operating conditions parameter symbol rating units conditions min typ max supply voltage v dd 3.0 3.3 3.6 v vdd,lvdsvdd,pllvdd operating temperature range topr -20 - 85 clock frequency from 8mhz up to 90mhz 0 - 70 cock frequency from 90mhz up to 112mhz
7 / 20 dc characteristics table 5 : lvcmos dc specifications v dd =3.0v3.6v, ta=-2085 symbol parameter rating units conditions min typ max v ih high level input voltage v dd 0.8 - v dd v exclude rs pin v il low level input voltage gnd - v dd 0.2 v v ihrs high level input voltage v dd 0.8 - v dd rs pin v ilrs low level input voltage gnd - 0.2 v ddq *1 small swing voltage 1.2 - 2.8 v v ref input reference voltage - v ddq /2 - - small swing(rs=v ddq /2) v sh *2 small swing high level input voltage v ddq /2 +200mv - - v v ref =v ddq /2 v sl *2 small swing low level input voltage - - v ddq /2 -200mv v v ref =v ddq /2 i inc input current - - 10 a 0v v in v dd *1: v ddq voltage defines max voltage of s mall swing input. it is not an actual input voltage. *2: small swing signal is app lied to ta[6:0], tb[6:0], tc[6 :0], td[6:0] te[6:0], clkin. table 6 : lvds transmi tter dc specifications v dd =3.0v3.6v, ta=-2085 symbol parameter rating units conditions min typ max v od differential output voltage 250 350 450 mv rl=100 normal swing rs=v dd 100 200 300 mv reduced swing rs=gnd v od change in vod between complementary output states - - 35 mv rl=100 v oc common mode voltage 1.125 1.25 1.375 v v oc change in voc between complementary output states - - 35 mv i os output short circuit current - - -24 ma v out =0v, rl=100 i oz output tri-state current - - 10 a xrst=0v, v out =0v to v dd
8 / 20 supply current table 7 : supply current symbol parameter rating units conditions typ max i tccg transmitter supply current 57 - ma rl=100,cl=5pf v dd =3.3v,rs=v dd gray scale pattern f=85mhz 42 - ma rl=100,cl=5pf v dd =3.3v,rs=gnd gray scale pattern f=85mhz i tccw transmitter supply current 62 - ma rl=100,cl=5pf v dd =3.3v,rs=v dd worst case pattern f=85mhz 45 - ma rl=100,cl=5pf v dd =3.3v,rs=gnd worst case pattern f=85mhz i tccs transmitter power down supply current - 10 a xrst=l
9 / 20 gray scale pattern figure-4 gray scale pattern worst case pattern (maximum power condition) figure-5 worst case pattern clkout rx0 rx1 rx2 rx3 rx4 rx5 rx6 x=a,b,c,d,e clkout rx0 rx1 rx2 rx3 rx4 rx5 rx6 x=a,b,c,d,e
10 / 20 ac characteristics table 8 : switching characteristics symbol parameter min typ max units t tcit clk in transition time - - 5.0 ns t tcp clk in period 8.93 - 125.0 ns t tch clk in high time 0.35t tcp 0.5t tcp 0.65t tcp ns t tcl clk in low time 0.35t tcp 0.5t tcp 0.65t tcp ns t tcd clk in to tclk+/-delay - t tcp - ns t ts lvsmos data set up to clk in 2.5 - - ns t th lvcmos data hold from clk in 0 - - ns t lvt lvds transition time - 0.6 1.5 ns t top1 output data position 0 -0.2 0.0 +0.2 ns t top0 output data position 1 7 t tcp -0.2 7 t tcp 7 t tcp +0.2 ns t top6 output data position 2 2 7 t tcp -0.2 2 7 t tcp 2 7 t tcp +0.2 ns t top5 output data position 3 3 7 t tcp -0.2 3 7 t tcp 3 7 t tcp +0.2 ns t top4 output data position 4 4 7 t tcp -0.2 4 7 t tcp 4 7 t tcp +0.2 ns t top3 output data position 5 5 7 t tcp -0.2 5 7 t tcp 5 7 t tcp +0.2 ns t top2 output data position 6 6 7 t tcp -0.2 6 7 t tcp 6 7 t tcp +0.2 ns t tpll phase locked loop set time - - 10.0 ms
11 / 20 ac timing ac timing diagrams figure-6 ac timing diagrams lvcmos input clk in 90% 10% 90% 10% t tcit t tcit lvds output vdiff=(tap)-(tan) cl tan tap lvds output load rl v diff 80% 20% 80% 20% t lvt t lvt t tcp t t ch t tcl v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 t tcd v oc clkin tx0-tx6 tclkp tclkn t ts t th rf=l rf=h lvcmos input
12 / 20 small swing inputs figure-7 small swing inputs t tcp t tch t tcl v ddq /2 v ddq /2 t tcd v oc clkin tx0-tx6 tclkp tclkn t ts t th v ddq /2 v ref rf=l rf=h v ref v ddq gnd v ddq /2 v ddq /2
13 / 20 ac timing diagrams figure-8 ac timing diagrams phase locked loop set time figure-9 phase locked loop set time lvds output t top1 tap/n ta6 ta5 ta4 ta3 ta2 ta1 ta0 tbp/n tb6 tb5 tb4 tb3 tb2 tb1 tb0 tcp/n tc6 tc5 tc4 tc 3 tc2 tc1 tc0 tdp/n td6 td5 td4 td 3 td2 td1 td0 tep/n te6 te5 te4 te3 te2 te1 te0 t top0 t top6 t top5 t top4 t top3 t top2 previous cycle next cycle tclk out (differential) 2.0v 3.0v 3.6v t tpll xrst v dd tclkp/n clkin v diff =0v
14 / 20 about the power on reset power on reset is not mandatory for this device. the pd pin should be set to high level when power on reset pro cedure is not used. however, power on reset procedure is strongly recommend for int ernal logic initialization by following two methods. the method of using cr circuit. the method of using external specific ic. it is recommend to do enough examination for target application . be careful of temperature of the capacitor especially over and again. b characteristic ceramics and polymer aluminum are recommended. BU8254KVT v dd figureC11 power on reset by external a cr circuit figureC12 power on reset by specific ic t d is approximately equal to 20ms when the left rc coleus are appl ied. t d v dd internal reset 2.2f xrst xrst 10k 220 v t + v dd v dd xrst v dd detection voltage v dd internal reset xrst vout gnd 220k 0.1f b characteristic ceramics. t d v t + v dd v dd xrst figureC10 terminal connection when power on reset is not used schottky barrier diode power on ic (open drain output)
15 / 20 if rs pin is tied to v dd , lvds swing is 350m v. if rs pin is tied to gnd , lvds swing is 200m v. 10bit lvcmos level input example: bu7986kut falling edge normal swing dual-in / dual-out mode vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf r1[9:0] v dd bu7986kut g1[9: 0] b1[9:0] r2[9:0] g2[9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 mode0 mode1 test[3:0] xrst rs r/f *1 lvds gnd ta1n ta1p tb1n tb1p tc1n tc1p tclkn tclkp td1n td1p te1n te1p pcb(transmitter) 100otwist pair cable or pcb trace r1[9:0] g1[ 9: 0] b1[9:0] r2[9:0] g2[ 9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 ta2n ta2p tb2n tb2p tc2n tc2p tclkn tclkp td2n td2p te2n te2p xrst v dd *1 :
16 / 20 if rs pin is tied to v dd , lvds swing is 350m v. if rs pin is tied to gnd , lvds swing is 200m v. 10bit lvcmos level input example: bu7986kut falling edge normal swing dual-in / single-out mode vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf r1[9:0] v dd bu7986kut g1[9: 0] b1[9:0] r2[9:0] g2[9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 mode0 mode1 test[3:0] xrst rs r/f *1 lvds gnd ta1n ta1p tb1n tb1p tc1n tc1p tclkn tclkp td1n td1p te1n te1p pcb(transmitter) 100otwist pair cable or pcb trace r1[9:0] g1[ 9: 0] b1[9:0] r2[9:0] g2[ 9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 ta2n ta2p tb2n tb2p tc2n tc2p tclkn tclkp td2n td2p te2n te2p xrst v dd v dd open *1 :
17 / 20 if rs pin is tied to v dd , lvds swing is 350m v. if rs pin is tied to gnd , lvds swing is 200m v. 10bit lvcmos level input example: bu7986kut falling edge normal swing single-in / dual-out mode vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf r1[9:0] v dd bu7986kut g1[9: 0] b1[9:0] r2[9:0] g2[9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 mode0 mode1 test[3:0] xrst rs r/f *1 lvds gnd ta1n ta1p tb1n tb1p tc1n tc1p tclkn tclkp td1n td1p te1n te1p pcb(transmitter) 100otwist pair cable or pcb trace r1[9:0] g1[ 9: 0] b1[9:0] hsync vsync de clk_in cont11 cont12 ta2n ta2p tb2n tb2p tc2n tc2p tclkn tclkp td2n td2p te2n te2p xrst vdd v dd *1 :
18 / 20 if rs pin is tied to v dd , lvds swing is 350m v. if rs pin is tied to gnd , lvds swing is 200m v. 10bit lvcmos level input example: bu7986kut falling edge normal swing single-in / single -out mode vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf r1[9:0] v dd bu7986kut g1[9: 0] b1[9:0] r2[9:0] g2[9: 0] b2[9:0] hsync vsync de clk_in cont11 cont12 cont21 cont22 mode0 mode1 test[3:0] xrst rs r/f *1 lvds gnd ta1n ta1p tb1n tb1p tc1n tc1p tclkn tclkp td1n td1p te1n te1p pcb(transmitter) 100otwist pair cable or pcb trace r1[9:0] g1[ 9: 0] b1[9:0] hsync vsync de clk_in cont11 cont12 ta2n ta2p tb2n tb2p tc2n tc2p tclkn tclkp td2n td2p te2n te2p xrst v dd open v dd v dd *1 :
19 / 20 *3 : recommended parts: f.bead : blm18a-series (murata manufacturing) *4 : rs pin acts as vref input pi n when input voltage is set to half of high leve l signal input. we recommend to locate by-pass condenser near the rs pin. 10bit small swing input example: BU8254KVT lvcmos level input /falling edge/normal swing bu8255kvt falling edge vdd gnd 0.1uf lvds vdd 0.01uf 0.1uf 0.01uf clkin v dd f.bead clkin BU8254KVT ta0 r4 ta1 r5 ta2 r6 ta3 r7 ta4 r8 ta5 r9 ta6 g4 tb0 g5 tb1 g6 tb2 g7 tb3 g8 tb4 g9 tb5 b4 tb6 b5 tc0 b6 tc1 b7 tc2 b8 tc3 b9 tc4 hsync tc5 vsync tc6 de td0 r2 td1 r3 td2 g2 td3 g3 td4 b2 td5 b3 td6 te0 r0 te1 r1 te2 g0 te3 g1 te4 b0 te5 b1 te6 xrst xrst *4 rs r/f *4 lvds gnd pll vdd pll gnd 0.1uf 0.01uf tan tap tbn tbp tcn tcp tclkn tclkp tdn tdp ten tep pcb(transmitter) pcb(receiver) 100 100 100 100 100 100 ra- ra+ rb- rb+ rc- rc+ rclk- rclk+ rd- rd+ re- re+ 100twist pair cable or pcb trace 0.1uf 0.01uf 0.1uf 0.01uf lvdd lgnd pvdd pgnd f.bead bu8255kvt vdd gnd 0.1uf 0.01uf v dd clkout r4 r5 r6 r7 r8 r9 g4 g5 g6 g7 g8 g9 b4 b5 b6 b7 b8 b9 hsync vsync de r2 r3 g2 g3 b2 b3 r0 r1 g0 g1 b0 b1 pd clkout ra0 ra1 ra2 ra3 ra4 ra5 ra6 rb0 rb1 rb2 rb3 rb4 rb5 rb6 rc0 rc1 rc2 rc3 rc4 rc5 rc6 rd0 rd1 rd2 rd3 rd4 rd5 rd6 re0 re1 re2 re3 re4 re5 re6 dk r/f open open pd oe oe *3 *3 rs pin. 15k v dd r1 r2 c1=0.1uf 5.6k example for lvcmos(1.8v input):(r1,r2)=(15k,5.6k)
catalog no.08t240a '08.6 rohm ? when you order , please order in times the amount of package quantity. containe r quantit y direction of feed tray(with dry pack) 1000pcs direction of product is fixed in a tray. 1pin 1pin unit:mm) unit:mm) t q fp64v 0.1 33 48 16 1 12.0 0.3 10.0 0.2 0.125 0.1 0.5 0.2 0.1 0.1 0.1 1.0 0.1 0.5 49 64 32 17 10.0 0.2 12.0 0.3 t q fp64v

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